The invention relates to a method of manufacturing integrated circuits as described in the precharacterizing part of claim 1. The invention also relates to a system implementing said method.
Such a method is known from the abstract of Japanese patent application laid open number 5-259015 (1993).
Integrated circuits are manufactured by submitting wafers to a series of processing steps. During processing defects may occur on the wafer, which reduce the yield of properly functioning integrating circuits on the wafer. Malfunctioning apparatuses may increase the number of defects. The abstract of Japanese patent application laid open number 5-259015 (1993) proposes to count the number of defects such as particles or patterning errors on the wafer after a processing step. If the number of defects is to high, it is attempted to redo the processing step in order to remove the defects. If this is not possible, the wafer is discarded and the process conditions are adjusted before processing further wafers.
Such a method may be used in factory management system to increase the yield and to control the correction of malfunctioning apparatuses. However, if such a method is applied at each processing step to check for malfunctioning of the apparatus performing that processing step, the factory management system would become very expensive, even if it were possible without disturbing the processing steps. Moreover, in general there is no certainty that defects detected after a processing step are actually due to the apparatus performing that processing step: the defects might be due to apparatuses that perform earlier processing steps.